Machine Cycles and Timing

Instruction cycle → machine cycle → T-state. A machine cycle is exactly one bus transaction, taking three to six T-states. Counting machine cycles counts memory accesses, which is what actually costs time.

Sixteen address lines plus eight data lines will not fit in a 40-pin package alongside power and control. So AD0–AD7 carry the low address byte and then the data byte, and everything complicated about 8085 timing exists to disambiguate that sharing.

ALE goes high during T1 to announce that AD0–AD7 currently carry an address. An external 74LS373 latch captures it on ALE's falling edge and holds it, freeing the pins for data. One cheap chip in exchange for eight pins on the expensive one.

1. 1T1 — full 16-bit address presented; ALE pulses; the latch captures the low byte.
2. 2T2 — RD̄ goes low, telling memory to drive the data bus.
3. 3T3 — the processor samples AD0–AD7 and RD̄ returns high.
4. 4Throughout — IO/M̄ says whether this is memory or I/O, separating the two address spaces.

The memory has from mid-T2 to mid-T3 to produce its data. That window is its access-time specification, and it is the number you check against a memory chip's datasheet.

If memory cannot respond in time it holds READY low, and the processor inserts wait states between T2 and T3 — freezing the bus signals until the data is ready.

Slow memory works, at the cost of extra cycles on every access. That is why memory latency shows in system performance even when the processor is fast, and it is the direct ancestor of every modern memory-controller stall.

Instruction timing is memory traffic. Optimising small-processor assembly is largely a matter of reducing accesses, not of choosing clever instructions.

A timing diagram is a contract between chips. It tells the designer how fast the memory must be and whether wait states are needed, and it is exactly what a logic analyser displays when something is wrong.

Its real content is setup and hold times — data stable before and after the sampling edge. Violating either produces intermittent faults that look like software bugs and are not. Modern buses are far faster and the reasoning is unchanged.