Buses, Registers and Flags
The address bus width IS the address space — which is why 32-bit systems could never use more than 4 GB, and no operating system could work around it.
Skip to the animationA processor connects to the world through address, data and control buses, and the address bus width alone fixes the addressable memory at 2ⁿ — a hardware limit no software can exceed, which is why 32-bit systems could never use more than 4 GB.
Three buses
- Address bus
- One-way, CPU to memory. Says where. Its width fixes the address space.
- Data bus
- Bidirectional. Says what. Its width fixes how much moves per transfer.
- Control bus
- Assorted signals. Says when and which direction — read, write, memory or I/O.
Width decides everything
| Address lines | Address space | Processor |
|---|---|---|
| 16 | 64 KB | 8085, Z80 |
| 20 | 1 MB | 8086 — hence segmentation |
| 32 | 4 GB | The ceiling an entire generation hit |
| 64 | 16 EB | Effectively unlimited for now |
n address lines select 2ⁿ locations, and nothing in software can exceed that. It is a hardware limit, which is why no operating system could work around the 4 GB barrier.
The data bus is independent. "How many bits is this processor" usually refers to the data bus or the registers — which is why the 8088, with the 8086's 16-bit registers on an 8-bit data bus, was still called a 16-bit processor.
The registers
- Program counter (PC)
- The address of the next instruction. Incremented automatically; changed by a jump.
- Instruction register (IR)
- Holds the opcode while it is decoded. Not programmer-visible.
- Accumulator
- One operand in, and the result out. The 8085's ALU works through it.
- Stack pointer (SP)
- The top of the stack. What makes subroutines and interrupts possible at all.
- General-purpose registers
- B, C, D, E, H, L on the 8085. Scratch space that avoids memory.
A register access takes one cycle; a memory access takes several. That gap is the entire reason registers exist, and why compilers work so hard at register allocation.
Flags
Flags are single bits set by the ALU as a side effect of every arithmetic operation: Z (result was zero), S (sign), C (carry), P (parity), AC (auxiliary carry, for BCD).
A compare is a subtraction whose result is discarded and whose flags are kept. A conditional jump then tests one of them. That two-instruction pattern is what every if-statement in every language compiles down to.
Von Neumann and Harvard
| Von Neumann | Harvard | |
|---|---|---|
| Memory | One, shared by code and data | Separate code and data memories |
| Buses | One set — instructions and data take turns | Two sets — both in the same cycle |
| Self-modifying code | Possible | Not possible |
| Typical of | General-purpose computers | Microcontrollers and DSPs |
Modern processors are hybrids: von Neumann in main memory, Harvard in their split instruction and data caches. The bottleneck the split addresses is real, and both organisations are used where each fits.
Why clock speed lies
The hierarchy is clock cycle (T-state) → machine cycle → instruction. An 8085 MOV between registers takes 4 T-states; anything touching memory takes 7 or more.
So instruction timing varies by a factor of four or more, and clock rate alone tells you very little about how fast a program runs. Comparing processors by megahertz has always been misleading, and the reason is this hierarchy.
The numbers you will be asked for
- Address space
locations = 2ⁿ
n address lines
- 8085
16 address, 8 data → 64 KB
- 8086
20 address, 16 data → 1 MB
- Timing hierarchy
instruction ⊃ machine cycle ⊃ T-state
Watch it work
Check yourself
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