Direct Memory Access

Interrupt-driven I/O stops the processor polling, but the data still passes through it: read into a register, write out to memory, repeat. For one keypress that is negligible. For a 4 KB disk sector it is thousands of instructions doing nothing but copying.

1. 1The controller asserts HOLD, requesting the buses.
2. 2The processor finishes its current bus cycle.
3. 3It tristates its bus drivers and acknowledges with HLDA.
4. 4The controller drives the buses, moves the data, and releases them.

Note what does not happen: no context is saved, because no program state changes. The processor is suspended rather than interrupted, which is why DMA costs far less per byte than an interrupt would.

Cycle stealing is the usual compromise, and the name describes it exactly. A disk read wants cycle stealing; a video refresh that must never stutter wants burst; a background copy can afford transparent.

The processor writes a source address, a destination address, a byte count and a mode, then starts the controller. The controller counts down and raises an interrupt when it reaches zero.

That setup is a fixed cost amortised over the whole transfer — which is exactly why DMA is right for a 4 KB disk block and pointless for a single byte.

DMA writes memory behind the processor's back, so any cached copy becomes stale with nothing to signal it. The fixes are to mark DMA buffers non-cacheable, or to have the cache snoop bus traffic and invalidate affected lines.

Cache coherence hardware exists largely because of DMA and multiprocessing. On a microcontroller without caches the same class of bug appears when a compiler optimises away a re-read of a buffer — which is what volatile is for.

• Bus mastering — the controller is inside the device. A PCIe card moves data with no separate DMA chip.
• Scatter-gather — a list of blocks, so one setup covers a fragmented buffer.
• IOMMU — address translation and protection for device transfers.

The IOMMU matters because an unmediated bus master can write any physical address. DMA attacks over Thunderbolt and FireWire are real, so the mechanism that made I/O fast also created a security boundary that had to be rebuilt.